(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing resistance and increasing effective polysilicon width for a narrow polysilicon line in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, a silicide is often formed on top of a polysilicon gate and overlying the source and drain regions within a substrate. Typically, a titanium layer is deposited over the wafer. The wafer is subjected to a thermal process which causes the underlying silicon to react with the titanium layer to form titanium silicide. FIG. 16 illustrates a partially completed integrated circuit device of the prior art. A gate electrode 16 has been formed on the surface of a semiconductor substrate 10. Source and drain regions 20 have been formed within the substrate. Sidewall spacers 18 are typically composed of silicon dioxide or silicon nitride. A layer of titanium 24 is deposited over the surface of the wafer. A rapid thermal process causes the silicon atoms within the polysilicon gate and the substrate to diffuse into the titanium layer and react with the titanium to form titanium silicide 26, as illustrated in FIG. 17. The titanium layer 24 over the sidewall spacers 18 and the field oxide regions 12 is not reacted and can be removed easily. However, silicon from the gate and from the substrate can diffuse into the titanium layer overlying the sidewall spacers causing titanium silicide 28 to form overlying the spacers as well. This is the so-called bridging problem. The titanium silicide layer 28 over the spacers shorts the source/drain to the gate leading to malfunction of the device.
The salicide process is used to lower resistance and therefore improve device performance and reduce chip size. However, resistance is increased dramatically for narrow polysilicon lines, such as less than 0.25 .mu.m. This is caused by polysilicon critical dimension variation and non-uniform salicide thickness.
U.S. Pat. No. 5,648,287 to Tsai et al teaches two sets of silicon oxide spacers on the sidewalls of a gate, and a nitrogen-implanted amorphous silicon layer overlying the gate and source/drain regions. The nitrogen-rich layer acts as an oxidation barrier. U.S. Pat. No. 4,912,061 to Nasr shows a salicidation process using disposable silicon nitride spacers. U.S. Pat. No. 5,091,807 to Sanchez uses polysilicon and oxide spacers before salicidation. U.S. Pat. No. 5,658,807 to Manning teaches a method of salicidation of the sidewalls of a polysilicon gate. U.S. Pat. No. 4,716,131 to Okazawa et al teaches salicidation of the polysilicon sidewalls and source and drain regions first followed by a second salicidation of the top of the polysilicon gate.